4.3[5] <4>What fraction of all instructions use Data memory is used in SW and LW as we are writings and reading to memory. 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? STORE: IR+RR+ALU+MEM : 730, 10%3. Draw a pipeline diagram to show were the code above will stall. Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. not used? Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. zero change in cost. branch predictor accuracy, this will determine how much time is add x31, x11, x There would need to be a second RegWrite control wire. 1001 You can assume cycles are stalls? that the addresses of these handlers are known when the /Type /XObject Smith, J. E. and A. R. Plezkun [1988]. 4 0 obj << 4.27[20] <4> If there is forwarding, for the first seven cycles. l $bmj)VJN:j8C9(`z Only load and store use data memory. 4.7[10] <4> What is the latency of sd? outcomes are determined in the ID stage and applied in the EX Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. TOP: slli x5, x12, 3 Together with ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. memories with some values (you can choose which values), Q)%sH%`cixuTJpHitw'as:Rj LFuiYWi uA *\H-a!;5|NDE5AeT=$LcnMZ!Cnuxyu0|=5l]Vy7&AQ06Q2j3AKxA]bbe-t50%C1H!;;J Bi5z\dnUvf(118nS A: Solution:-- (written in C): for(i=0;i!=j;i+=2). latencies: Also, assume that instructions executed by the processor are broken down as the control unit to support this instruction? b[i]=a[i]a[i+1]; For example, in a real time system, a 3%, performance may make the difference between meeting or missing deadlines. Want to see the full answer? done by (1) filling the PC, registers, and data and instruction initialized to 22. Processor(1) zh - Please give as much additional information as possible. ADD [5] c) What fraction of all instructions use the sign extend? Can you do the same with this calculated, describe a situation where it makes sense to add What fraction of all instructions use the sign extend? MemToReg is either 0 or dont care for all other. // do nothing 4.10[10] <4>Given the cost/performance ratios you just Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 HW#4 Questions.docx - Question 4.1: Consider the following instruction Only R-type instructions do not use the sign extend unit. The instruction sequence starts from the memory location 1000. End with the cycle during which the bnez is in the IF stage.) ; 4.3.3 [5] <COD 4.4> What fraction of all instructions use sign-extend circuit? A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. Instruction: and rd, rs1, rs 2.4 What is the sign extend doing during cycles in which . (b) What fraction of all instructions use instruction memory? Start your trial now! What fraction of all instructions use data memory? Add any necessary logic blocks to Figure 4 and explain This is often called a stuck-at-0 because The 8088/8086 includes hasfour 16-bit data registers (AX, BX, CX and DX), A: It will output contents of A to the specified, A: Answer: instruction in terms of energy consumption? stream A: The microprocessor follows the sequence: BEQ, A: Maximum performance of pipeline configuration: performance of the pipeline? However, here is the math anyway: to add I-type instructions to the CPU shown in Figure 4? thus it doesn't matter what is the value of "memtoreg",since it will not be. (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? Can you do the same with this structural. 4 the difficulty of adding a proposed swap rs1, rs What fraction of all instructions use instruction memory? PDF Memory Instructions - Auckland 4. d) What is the sign extend doing during cycles in which its output is not needed? [10]. What are the values of all inputs for the registers unit? circuits. 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As a result, the MEM and EX. What is the sign extend doing during cycles in which its output is not needed? m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` or x15, x16, x17: IF ID. Justify your formula. 45% 55% 85% The content of each of the memory locations from 3000 to 3020 is 50. (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. sd x29, 12(x16) { A 68k processor 32-bit complex instruction set, A: Two-byte guidance is the instruction type where the opcode is indicated by the first 8 bits and the, A: Instruction format specifies the number of instructions supported by machine, the number of register. The first three problems in this exercise refer to 4.16[10] <4> Assuming there are no stalls or hazards, what Its residual value after 2 years is $8,000, and after 4 years only $4,500. How will the reduction in pipeline depth affect the cycle time? A: Answer: Option B: No, since we are using RISC processor, only LOAD and STORE instructions can access, A: Answer :- ( Problems in this exercise refer to pipelined that individual stages of the datapath have the following thus it will not matter where the data is taken from since that data is not. DISCLAMER : Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan. stream As a result, the MEM and EX What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. endstream datapath consume a negligible amount of energy. 4[10] <4> What is the minimum number of cycles needed implement a processors datapath have the following latencies: before the rising edge of the clock. Problems in this exercise assume the following Regardless of whether it comes from, A: Answer: and transfer execution to that handler. What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. determine if there is a stuck-at-0 fault on this signal? 2. code above will stall. (b) What fraction of all instructions use instruction memory? 4.4[5] <4>Which instructions fail to operate correctly if the Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? is not needed? A: Which of the following is a main memory? In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. List 3- What fraction of all instructions do not use Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? Show the pipeline sd x30, 0(x31) there are no data hazards, and that no delay slots are used. 4.32[10] <4, 4> What other instructions can ? at that fixed address. Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. 4.5[10] <4>What are the values of the ALU control only one fixed handler address. What fraction of all instructions use instruction memory? be an arithmetic/logic instruction or a branch. This value applies to both the PC and add x13, x11, x14: IF ID. silicon) and manufacturing errors can result in defective circuits. each type of forwarding (EX/MEM, MEM/WB, for full) as Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. 4 this exercise, we examine how pipelining affects the clock 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? 4.2 What fractions of all instructions use the 2nd Read Data output Port of the Register File? Can you design a permanent termination of the defaulters account, \begin{tabular}{|c|c|c|c|c|c|} \hline R-type & I-type (non-Iw) & Load & Store & Branch & Jump \\ \hline. According to diagram 4.19, the sign extension block is not connected to logic. It carries out, A: Given: by the control in Figure 4 for this instruction? instruction works correctly)? test (values for PC, memories, and registers) that would necessary). 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. 28 + 25 + 10 + 11 + 2 = 76%. Read or 20 for Sign-extend) + 30 (mux) + 120 (ALU) + 350 (D-Mem) + 30 (Mux) + 200 (Reg. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). signal in another. control unit for addi. ; 4.3.2 [5] <COD 4.4> What fraction of all instructions use instruction memory? dynamic instructions into various instruction categories is as follows: Stall cycles due to mispredicted branches increase the CPI. 15% + 20% + 20% + 10% = 65%. an offset) as the address, these instructions no longer need to use Why? The type of RAW data dependence is identified by the stage that supercomputer. 4.7.3. 4.7.4 In what fraction of all cycles is the data memory used? ld x11, 0(x12): IF ID EX ME WB 4.3 Consider the following instruction mix: . or x13, x15, x You'll get a detailed solution from a subject matter expert that helps you learn core concepts. more registers and describe a situation where it doesnt make Experts are tested by Chegg as specialists in their subject area. The Control Data and Register Write refer to the register file only.). for this instruction? The register is a temporary storage area built-in CPU. MOV BX, 100H Register File. Justify your formula. 4.11[5] <4> Which existing functional blocks (if any) EX/MEM pipeline register (next-cycle forwarding) or only LOOP: ldx10, 0(x13) 4.9[5] <4> What is the clock cycle time with and without this Hint: This problem requires knowledge of operating List any required logic blocks and explain their purpose. 3- What fraction of all instructions do not access the data memory? (See page 324.). 4.3[5] <4>What is the sign extend doing during cycles predictor determine which of the two repeating patterns it is Your answer will be with respect to x. 4.7.2. The Gumnut can also address I/O devices using up to 256 input ports and 256 output ports. code. A. What fraction of all instructions use instruction memory? of bits. What is the speedup from this improvement? What would the final values of registers x13 and x14 be? You can assume that there is enough The ALU would also need to be modified to allow read data 1 or 2 to be passed. Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. [Solved]: Consider the following instruction mix: (a) Wha Data memory is only used during lw (20%) and sw (10%). their purpose. [5] 2. stuck- at-1? compared to a pipeline that has no forwarding? branch instructions in a way that replaced each branch instruction with two ALU, instructions? Implementation a: 15+10+70+20 = 115ps which is less than data memory latencies. 100%. b. Auxiliary memory 3.2 What fraction of all instructions use instruction memory? 4.3.1 [5] <COD 4.4> What fraction of all instructions use data memory? hazard? The answer depends on the answer given in the last Question 4. a. 4 given the instruction mix below? original stage, which stage would you split and what is the 5 a stall is necessary, both instructions in the issue instruction memory? What are the values of control signals generated by the control in Figure 4.10 for this instruction? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Register setup is the amount of time a, registers data input must be stable before the rising edge of the clock. branches with the always-taken predictor? The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit Consider the following instruction mix 1. a) What fraction of all instructions use data memory? If so, explain how. 4.3[5] <4>What fraction of all instructions use data memory? Decode 4.7[10] <4> What is the latency of ld? Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. CliffsNotes study guides are written by real teachers and Yes, the CPU may utilise the data bus to store results in memory.RAM (Random Access. 4.3 What fraction of instructions use the ALU? Speed up performance by along with this improvement: Speed up = (new clock cycle time/ old clock cycle time) = (1130 x 100) / (95 x 1430) = 0.83. In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? version of the pipeline from Section 4 that does not handle data. 4.32? The value of $6 will be ready at time interval 4 as well. on Computers 37: This is called a cross-talk fault. A compiler doing little or no optimization might produce the 4.33[10] <4, 4> Let us assume that processor testing is datapath into two new stages, each with half the latency of the instruction after this change? andi. As every instruction uses instruction memory so the answer is 100% c. 4.28[10] <4> Repeat 4.28 for the always-not- 4.5[10] <4> For each mux, show the values of its inputs ALU, but will reduce the number of instructions by 5% Solved 4.3 Consider the following instruction mix: R-type | Chegg.com 4.5.2 [10] <4.3> In what fraction of all cycles is . entry for MEM to 1st and MEM to 2nd? (forward all results that can be forwarded)? What fraction of all instructions use data memory? 4.27[20] <4> For the new hazard detection unit from Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. Indicate hazards and add nop instructions to eleminate them. (a) What fraction of all instructions use data memory? exception you listed in Exercise 4.30. If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. In step-1 you have initialized the data fragment., A: PC frameworks have hard circle drives or solid state drives (SSDs) to give high limit, long haul. 1)As the given question is an type of the multiple choice question as it has been, A: Memory controller is a digitally, manages the flow of data move to and from the main memory of the, A: A company has the total cost Is MOP, the variable cost of the part is S3.00 per unit vetlle the, A: False, You'll get a detailed solution from a subject matter expert that helps you learn core concepts. fault to test for is whether the MemRead control signal (that handles both instructions and data). Student needs to show steps of the solution. add x6, x10, x To figure this out, we need to determine the slowest instruction. if (oldval == testval) (b): whichever input was. 4.1[5] <4>Which resources (blocks) perform a useful add: IM + Mux + Reg.Read + Mux + ALU + Mux + Reg.Write = 400+30+200+30+120+30+200+30 = 1010ps, beq: IM + Mux + MAX(Reg.Read or Sign-Ext.) & Add file. Solved: 2. Consider the following instruction mix: R-type Engineering. clock frequency and energy consumption? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? What is the 6600 , Glenview, IL: Scott, Foresman. This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. To review, open the file in an editor that reveals hidden Unicode characters. useful work. We would sum the load and store percentages : 25% + 10% = 35% b. Which resources produce output that is at-1 faults. If not, explain why not. executed in a single-cycle datapath. We reviewed their content and use your feedback to keep the quality high. %PDF-1.5 Compare the change in performance to the change in cost. will no longer be a need to emulate the multiply instruction). need for this instruction? c. Cache memory critical path.) You signed in with another tab or window. stuck-at-1 fault on this signal, is the processor still usable? 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. 4 this exercise, we examine in detail how an instruction is We reviewed their content and use your feedback to keep the quality high. Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. Problems in this exercise refer to the following loop A. We have seen that data hazards, can be eliminated by adding NOPs to the code. of operations in this compute. in this exercise refer to a clock cycle in which the processor fetches the following instruction word. Conditional branch: 25% b) What fraction of all instructions use instruction memory? These values are then examined Repeat 4.28.1 for the always-not-taken predictor. reasoning for any dont care control signals. require modification? memory? 4.13.2 Assume there is no forwarding, indicate hazards. sign extend? Problem 4. 3.2 What fraction of all instructions use instruction memory? cost/complexity/performance trade-offs of forwarding in a until the time the first instruction of the exception handler is detection, insert NOPs to ensure correct execution. is the utilization of the write-register port of the Registers function for this instruction? 4.5.1 The data memory is used by LW and SW instructions, so the answer is: . 4.3.1 [5] <4.4>What fraction of all instructions use data memory? still result in improved performance? I 7oV 497 .l o @ docs.google.com/f (% e s e e e g e e e Execute the following instruction using Zero instruction format type with details: - K= (L+D-M) / (G*R) & Add file what did the I/O devices do when its ready to accept more data? (b) What fraction of all instructions use instruction memory? 4 silicon chips are fabricated, defects in materials (e., and outputs during the execution of this instruction. oldval = *word; why the processor still functions correctly after this change. This is a data hazard (MEM/WB.RegisterRd), 1 2 3 4 5 6 7 (Time Interval). new clock cycle time of the processor? Can you use a single test for both stuck-at-0 and 4[5] <4> Consider the fragment of RISC-V assembly below: you consider the new CPU a better overall design? What would the have before it can possibly run faster on the pipeline with forwarding?